1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a process of manufacturing a deep trench capacitor of a DRAM device.
2. Description of the Prior Art
Trench-capacitor DRAM devices are known in the art. A trench-storage capacitor typically consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor.
In general, the prior art method for fabricating a trench capacitor of a DRAM device may include several major manufacture phases as follows:
Phase 1: deep trench etching.
Phase 2: buried plate and capacitor dielectric (or node dielectric) forming.
Phase 3: first polysilicon deep trench fill and first recess etching.
Phase 4: collar oxide forming.
Phase 5: second polysilicon deposition and second recess etching.
Phase 6: collar oxide wet etching.
Phase 7: third polysilicon deposition and third recess etching.
Phase 8: shallow trench isolation (hereinafter referred to as “STI”) forming.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic cross-sectional diagrams showing several intermediate steps of forming a prior art deep trench capacitor, which are relative to the present invention. As shown in FIG. 1, a substrate 10 having a pad oxide layer 26 and a pad nitride layer 28 thereon is provided. After deep trench etching, an N+ buried plate 13 and a node dielectric layer 14 are sequentially formed in the deep trench. A first polysilicon deposition and recess process is then carried out to form a first poly layer (Poly1) at the bottom of the deep trench. A collar oxide layer 15 is formed on sidewall of the deep trench above Poly1. A second polysilicon deposition and recess process is then carried out to form a second poly layer (Poly2) atopPoly1. The collar oxide layer 15 that is not covered by Poly 2 is stripped off to expose the sidewall of the deep trench. Subsequently, as shown in FIG. 2, a third polysilicon deposition and recess process is carried out to form a third poly layer (Poly3) atopPoly 2 and collar oxide layer 15. Dopants of the heavily doped Poly 2 diffuse out through Poly 3 to the surrounding substrate 10 to form an annular shaped buried strap out diffusion regions 16 in the following thermal process. A conventional STI process is performed to isolate the two adjacent deep trench capacitors.
Please refer to FIG. 3. FIG. 3 is an enlarged schematic plane view showing the layout of the memory chip containing the trench capacitors made according to the prior art method as set forth in FIG. 1 and FIG. 2. The perspective buried strap out diffusion regions 16 encircling each of the trench capacitors 11 are also illustrated in FIG. 3, which are indicated with dash lines. As shown in FIG. 3, to achieve a maximum packing density, pairs of trench capacitors are arranged in very close distance.
Please refer to FIG. 4 to FIG. 6. FIG. 4 is an enlarged schematic plane view showing, in an ideal condition, the layout of the deep trench (DT) capacitors 11 and active area photoresist (AA photo) pattern without AA-DT misalignment. FIG. 5 is a schematic cross-sectional diagram showing the deep trench capacitor 11 and the AA photo along line NN″ of FIG. 4, before STI etching. FIG. 6 is a schematic cross-sectional diagram showing the deep trench capacitor 11 and the shallow trench isolation (STI) along line NN″ of FIG. 4. As shown in FIG. 4 and FIG. 5, in an ideal condition, the AA photo that is used to define active areas on the substrate and to define isolation shallow trenches to be etched into the substrate does not overlap with the annular buried strap out diffusion regions 16. As shown in FIG. 5, the AA photo is typically patterned on an intermediate dielectric layer such as a BSG layer using lithographic process known in the art. Using the AA photo and the BSG layer as an etching hard mask, STI trenches are etched into the substrate that is not masked by the AA photo pattern using dry etching such as RIE. After removing the remaining photoresist and BSG layer, STI fill material such as high-density plasma chemical vapor deposition (HDPCVD) oxide is then deposited into the STI trenches, followed by CMP planarization, thereby forming the structure as set forth in FIG. 6. It is noted that since the AA photo does not overlap with the buried strap out diffusion region of a neighboring deep trench capacitor in y direction, most of the buried strap out diffusion region surrounding the deep trench capacitor is etched away during the above-said STI process.
Please refer to FIG. 7 and FIG. 8. FIG. 7 is an enlarged schematic plane view showing, in a non-ideal condition, the layout of the deep trench (DT) capacitors 11 and active area photoresist (AA photo) pattern with AA-DT misalignment. FIG. 8 is a schematic cross-sectional diagram showing the deep trench capacitor 11 and the AA photo along line NN″ of FIG. 7. In practice, misalignment between the AA photo and the deep trench capacitors 11 usually occurs. As shown in FIG. 7, the AA photo shifts a distance in y direction. This causes AA photo to overlap with the buried strap out diffusion regions 16 of neighboring deep trench capacitors. As shown in FIG. 8, after STI formation, the masked buried strap out diffusion region 16, which is not etched away during the STI process, will adversely affect the active areas and transistor characteristics.